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CDCU877B 1.8-V PHASE LOCK LOOP CLOCK DRIVER
www.ti.com
SCAS801B - JUNE 2005 - REVISED JULY 2007
FEATURES
* * * * * * * 1.8-V Phase Lock Loop Clock Driver for Double Data Rate (DDR II) Applications Spread Spectrum Clock Compatible Operating Frequency: 10 MHz to 340 MHz Low Current Consumption: <115 mA Low Jitter (Cycle-Cycle): 30 ps Low Output Skew: 25 ps Low Period Jitter: 20 ps
* * * * *
*
Low Dynamic Phase Offset: 15 ps Low Static Phase Offset: 50 ps Distributes One Differential Clock Input to Ten Differential Outputs 52-Ball BGA (MicroStarTM Junior BGA, 0,65-mm pitch) External Feedback Pins (FBIN, FBIN) are Used to Synchronize the Outputs to the Input Clocks Fail-Safe Inputs
DESCRIPTION
The CDCU877B is a high-performance, low-jitter, low-skew, zero-delay buffer that distributes a differential clock input pair (CK, CK) to ten differential pairs of clock outputs (Yn, Yn) and to one differential pair of feedback clock outputs (FBOUT, FBOUT). The clock outputs are controlled by the input clocks (CK, CK), the feedback clocks (FBIN, FBIN), the LVCMOS control pins (OE, OS), and the analog power input (AVDD). When OE is low, the clock outputs, except FBOUT/FBOUT, are disabled while the internal PLL continues to maintain its locked-in frequency. OS (output select) is a program pin that must be tied to GND or VDD. When OS is high, OE functions as previously described. When OS and OE are both low, OE has no affect on Y7/Y7, they are free running. When AVDD is grounded, the PLL is turned off and bypassed for test purposes. When both clock inputs (CK, CK) are logic low, the device enters in a low power mode. An input logic detection circuit on the differential inputs, independent from input buffers, detects the logic low level and performs in a low power state where all outputs, the feedback, and the PLL are off. When the clock inputs transition from being logic low to being differential signals, the PLL turns back on, the inputs and the outputs are enabled, and the PLL obtains phase lock between the feedback clock pair (FBIN, FBIN) and the clock input pair (CK, CK) within the specified stabilization time. The CDCU877B is able to track spread spectrum clocking (SSC) for reduced EMI. This device operates from --40C to 85C. ORDERING INFORMATION
TA -40C to 70C (1) 52-BALL BGA
(1)
CDCU877BZQL
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. MicroStar is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 2005-2007, Texas Instruments Incorporated
CDCU877B 1.8-V PHASE LOCK LOOP CLOCK DRIVER
SCAS801B - JUNE 2005 - REVISED JULY 2007
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. MicroStar Junior (ZQL) Package (TOP VIEW)
GND GND Y1 Y0 Y5 Y0 Y5 Y6
5 6
1 A
2
3
4
Y1 GND Y2 GND Y2 VDDQ VDDQ CK VDDQ CK VDDQ AGND VDDQ VDDQ AVDD GND Y3 GND
B
Y6 GND
C
NB
NB
Y7 GND Y7 OS VDDQ
D
E
NB
NB
FBIN VDDQ FBIN OE FBOUT VDDQ VDDQ
F G
NB
NB
H
NB
NB
FBOUT GND Y8 GND
J
K
GND Y4
GND Y9
Y3
Y4
A. B.
NC = No Connection NB = No Ball
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Y9
Y8
CDCU877B
www.ti.com
1.8-V PHASE LOCK LOOP CLOCK DRIVER
SCAS801B - JUNE 2005 - REVISED JULY 2007
TERMINAL FUNCTIONS
TERMINAL NAME AGND AVDD CK CK FBIN FBIN FBOUT FBOUT OE OS GND VDDQ Y[0:9] Y[0:9] NO. G1 H1 E1 F1 E6 F6 H6 G6 F5 D5 B2, B3, B4, B5, C2, C5, H2, H5, J2, J3, J4, J5 D2, D3, D4, E2, E5, F2, G2, G3, G4, G5 A2, A1, D1, J1, K3, A5, A6, D6, J6, K4 A3, B1, C1, K1, K2, A4, B6, C6, K6, K5 O O I I I I O O I I I/O DESCRIPTION Analog ground Analog power Clock input with a (10 k to 100 k) pulldown resistor Complementary clock input with a (10 k to 100 k) pulldown resistor Feedback clock input Complementary feedback clock input Feedback clock output Complementary feedback clock output Output enable (asynchronous) Output select (tied to GND or VDD) Ground Logic and output power Clock outputs Complementary clock outputs
FUNCTION TABLE
INPUTS AVDD GND GND GND GND 1.8 V Nominal 1.8 V Nominal 1.8 V Nominal 1.8 V Nominal 1.8 V Nominal X OE H H L L L L H H X X OS X X H L H L X X X X CK L H L H L H L H L H CK H L H L H L H L L H Y L H LZ LZ Y7 Active LZ LZ Y7 Active L H LZ Y H L LZ LZ Y7 Active LZ LZ Y7 Active H L LZ OUTPUTS FBOUT L H L H L H L H LZ Reserved FBOUT H L H L H L H L LZ PLL Bypassed/Off Bypassed/Off Bypassed/Off Bypassed/Off On On On On Off
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CDCU877B 1.8-V PHASE LOCK LOOP CLOCK DRIVER
SCAS801B - JUNE 2005 - REVISED JULY 2007
www.ti.com
Figure 1. LOGIC DIAGRAM (POSITIVE LOGIC)
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CDCU877B
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1.8-V PHASE LOCK LOOP CLOCK DRIVER
SCAS801B - JUNE 2005 - REVISED JULY 2007 (1)
Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
MIN VCC VI VO IIK IOK IO Tstg (1) (2) (3) Supply voltage range Input voltage range (2) (3) Output voltage range Input clamp current Output clamp current Continuous output current Continuous current through each VDDQ or GND Storage temperature range -65
(2) (3)
MAX 2.5 2.5 VCC + 0.5 50 50 50 100 150
UNIT V V V mA mA mA mA C
VDDQ or AVDD VI VO VI < 0 or VI > VDDQ VO < 0 or VO > VDDQ VO = 0 to VDDQ
-0.5 -0.5 -0.5
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. This value is limited to 2.5 V maximum.
Recommended Operating Conditions
MIN VCC VI VIL VIH IOH IOL VIX VI VID TA (1) (2) Output supply voltage, VDDQ Supply Voltage, AVDD Input voltage (1) Low-level input voltage (2) High-level input voltage
(2)
NOM 1.8 VDDQ
MAX 1.9 VCC
UNIT V V V V V mA mA V V V V C
1.7
OE, OS CK, CK 0.65 x VDDQ
0.35 x VDDQ -9 9 (VDDQ/2) - 0.15 -0.3 0.3 0.63 -40 (VDDQ/2) + 0.15 VDDQ + 0.3 VDDQ + 0.4 VDDQ + 0.4 85
High-level output current Low-level output current (see Figure 2) Input differential-pair cross voltage (see Figure 2 ) Input voltage level Input differential voltage (see Figure 9 )
(2)
DC AC
Operating free-air temperature
The PLL is turned off and bypassed for test purposes when AVDD is grounded. During this test mode, VDDQ remains within the recommended operating conditions and no timing parameters are specified. VID is the magnitude of the difference between the input level on CK and the input level on CK, see Figure 9 for definition. The CK and CK, VIH and VIL limits define the dc low and high levels for the logic detect state.
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CDCU877B 1.8-V PHASE LOCK LOOP CLOCK DRIVER
SCAS801B - JUNE 2005 - REVISED JULY 2007
www.ti.com
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VIK VOH VOL IO(DL) VOD II IDD(LD) Input High-level output voltage Low-level output voltage Low-level output current, dissabled Differential output voltage (1) CK, CK Input current OE, OS, FBIN, FBIN CK and CK = L CK and CK = 270 MHz. All outputs are open (not connected to a PCB) IDD Supply current, dynamic (IDDQ + IADD) (see Note (2) for CPD calculation) All outputs are loaded with 2 pF and 120- termination resistor All outputs are loaded with 10 pF and 120- termination resistor CI CI() (1) (2) Input capacitance Change in input current CK, CK FBIN, FBIN CK, CK FBIN, FBIN VI = VDD or GND VI = VDD or GND TEST CONDITIONS II = 18 mA IOH = -100 A IOH = -9 mA IOL = 100 A IOL = 9 mA VO(DL) = 100 mV, OE = L 1.7 1.7 1.7 1.9 1.9 1.9 1.9 1.9 1.9 1.8 1.8 1.8 1.8 2 2 100 0.5 250 10 500 115 215 235 3 3 0.25 0.25 pF mA A A AVDD , VDDQ 1.7 1.7 to 1.9 1.7 VDDQ - 0.2 1.1 0.1 0.6 MIN TYP (1) MAX -1.2 UNIT V V V A V
Supply current, static (IDDQ + IADD)
VOD is the magnitude of the difference between the true and complimentary outputs. See Figure 9 for a definition. Total IDD = IDDQ + IADD = fCK x CPD x VDDQ, solving for CPD = (IDDQ + IADD)/(fCK x VDDQ) where fCK is the input frequency, VDDQ is the power supply, and CPD is the power dissipation capacitance.
Timing Requirements (1)
over recommended operating free-air temperature range (unless otherwise noted) (see )
PARAMETER fCK tDC tL (1) (2) (3) (4) Clock frequency (operating) (1) (2) Clock frequency (application) Duty cycle, input clock Stabiliztion time
(4) (1) (3)
TEST CONDITIONS
MIN 10 160 40%
MAX 340 340 60% 12
UNIT MHz MHz s
AVDD, VDD = 1.8 V 0.1 V
The PLL must be able to handle spread spectrum induced skew. Operating clock frequency indicates a range over which the PLL must be able to lock, but in which it is not required to meet the other timing parameters (used for low speed system debug). Application clock frequency indicates a range over which the PLL must meet all timing parameters. Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal after power up. During normal operation, the stabilization time is also the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal when CK and CK go to a logic low state, enter the power-down mode and later return to active operation. CK and CK may be left floating after they have been driven low for one complete clock cycle.
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CDCU877B
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1.8-V PHASE LOCK LOOP CLOCK DRIVER
SCAS801B - JUNE 2005 - REVISED JULY 2007
(1)
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see
PARAMETER ten tdis tjit(cc+) tjit(cc-) t() t()dyn tsk(o) tjit(per) Enable time, OE to any Y/Y Disable time, OE to any Y/Y Cycle-to-cycle period jitter (2) Static phase offset time (3) Dynamic phase offset time Output clock skew Period jitter
(4) (2)
) AVDD, VDD = 1.8 V 0.1 V
TYP MAX 8 8 UNIT ns ns ps ps ps ps ps
TEST CONDITIONS See Figure 11 See Figure 11 160 MHz to 200 MHz, see Figure 4 200 MHz to 270 MHz, see Figure 4 270 MHz to 340 MHz, see Figure 4 See Figure 5 See Figure 10 See Figure 6 160 MHz to 200 MHz, see Figure 7 201 MHz to 340 MHz, see Figure 7 160 MHz to 190 MHz, see Figure 8 190 MHz to 250 MHz, see Figure 8 250 MHz to 340 MHz, see Figure 8 See Figure 9 See Figure 9
MIN
0 0 0 -50 -15 -30 -20 90 60 40 0.5 1 1.5 (VDDQ/2) 0.1 30 0% 2 2.5 2.5
40 35 30 50 15 25 30 20
tjit(hper) Half-period jitter (4) (2) Slew rate, OE SR Input clock slew rate Output clock slew rate VOX
(5) (6)
ps
4 3 (VDDQ/2) + 0.1 33 -0.5%
V/ns
(no load)
(7)
See Figure 9 and Figure 13 See Figure 2
Output differential-pair cross voltage SSC modulation frequency SSC clock input frequency deviation PLL loop bandwidth
V kHz MHz
(1) (2) (3) (4) (5) (6)
(7)
There are two different terminations that are used with the following tests. The load/board in Figure 2 is used to measure the input and output differential-pair cross voltage only. The load/board in Figure 3 is used to measure all other tests. For consistency, equal length cables must be used. This parameter is specifieded by design and characterization. Phase static offset time does not include jitter. Period jitter, half-period jitter specifications are separate specifications that must be met independently of each other. The output slew rate is determined from the IBIS model with a 120- load only. To eliminate the impact of input slew rates on static phase offset, the input skew rates of reference clock input CK and CK and feedback clock inputs FBIN and FBIN are recommended to be nearly equal. The 2.5-V/ns skew rates are shown as a recommended target. Compliance with these typical values is not mandatory if it can adequately shown that alternative characteristics meet the requirements of the registered DDR2 DIMM application. Output differential-pair cross voltage specified at the DRAM clock input or the test load.
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CDCU877B 1.8-V PHASE LOCK LOOP CLOCK DRIVER
SCAS801B - JUNE 2005 - REVISED JULY 2007
www.ti.com
PARAMETER MEASUREMENT INFORMATION
VDD CU877B GND C = 10 pF Z = 60 W L = 2.97" Z = 120 W Z = 60 W L = 2.97" C = 1 pF C = 10 pF GND VTT Note: VTT = GND R = 1 MW C = 1 pF VTT R = 1 MW SCOPE
Figure 2. Output Load Test Circuit 1
VDD/2 CU877B -VDD/2 C = 10 pF Z = 60 W L = 2.97" R = 10 W Z = 50 W R = 50 W Z = 50 W R = 10 W R = 50 W C = 10 pF -VDD/2 -VDD/2 VTT Note: VTT = GND VTT SCOPE
Z = 60 W L = 2.97"
Figure 3. Output Load Test Circuit 2
Yx, FBOUT Yx, FBOUT tcycle n tjit(cc) = tcycle n - tcycle n+1 tcycle n+1
Figure 4. Cycle-To-Cycle Period Jitter
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CDCU877B
www.ti.com
1.8-V PHASE LOCK LOOP CLOCK DRIVER
SCAS801B - JUNE 2005 - REVISED JULY 2007
PARAMETER MEASUREMENT INFORMATION (continued)
tjn
Figure 5. Static Phase Offset
n=N N
tjn+1
a1 tj =
tjn
(N is the large number of samples) (N > 1000 samples)
(1)
Figure 6. Output Skew
Figure 7. Period Jitter
t jit(per) = tcycle n 1 fO
(2)
(fO average input frequency measured at CK/CK
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CDCU877B 1.8-V PHASE LOCK LOOP CLOCK DRIVER
SCAS801B - JUNE 2005 - REVISED JULY 2007
www.ti.com
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 8. Half-Period Jitter
t jit(hper) = thalf period n n = any half cycle (fO average input frequency measured at CK/CK
1 2 x fO
(3)
80%
80%
VID, VOD
Clock Inputs and Outputs, OE
20% 20%
tr(i), tr(o)
tf(i), tf(o)
Figure 9. Input and Output Slew Rates
slrr(i/o) = V80% - V20% tr(i/o) slrf(i/o) = V80% - V20% t f(i/o)
(4)
tj tjdyn tjdyn tjdyn
tj tjdyn
Figure 10. Dynamic Phase Offset
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CDCU877B
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1.8-V PHASE LOCK LOOP CLOCK DRIVER
SCAS801B - JUNE 2005 - REVISED JULY 2007
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 11. Time Delay Between OE and Clock Output (Y, Y) RECOMMENDED AVDD FILTERING
CARD VIA Bead 0603
AV DD
V DDQ
1W 4.7 mF 1206 0.1 mF 0603 2200 pF 0603
PLL
GND
CARD VIA
A. B. C. Place the 2200-pF capacitor close to the PLL. Use a wide trace for the PLL analog power and ground. Connect PLL and capacitors to AGND trace and connect trace to one GND via (farthest from the PLL). Recommended bead: Fair-Rite PN 2506036017Y0 or equilvalent (0.8 dc maximum, 600 at 100 MHz).
AGND
Figure 12. Recommended AVDD Filtering
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CDCU877B 1.8-V PHASE LOCK LOOP CLOCK DRIVER
SCAS801B - JUNE 2005 - REVISED JULY 2007
www.ti.com
PARAMETER MEASUREMENT INFORMATION (continued)
VDD CDCU877B
VCK
R = 60 W
R = 60 W
VDD/2
VCK
Figure 13.
12
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PACKAGE OPTION ADDENDUM
www.ti.com
3-Jul-2007
PACKAGING INFORMATION
Orderable Device CDCU877BZQLR Status (1) ACTIVE Package Type BGA MI CROSTA R JUNI OR BGA MI CROSTA R JUNI OR Package Drawing ZQL Pins Package Eco Plan (2) Qty 52 1000 Green (RoHS & no Sb/Br) Lead/Ball Finish SNAGCU MSL Peak Temp (3) Level-2-260C-1 YEAR
CDCU877BZQLT
ACTIVE
ZQL
52
250
Green (RoHS & no Sb/Br)
SNAGCU
Level-2-260C-1 YEAR
(1)
The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Feb-2008
TAPE AND REEL BOX INFORMATION
Device
Package Pins
Site
Reel Diameter (mm) 330 330
Reel Width (mm) 16 16
A0 (mm)
B0 (mm)
K0 (mm)
P1 (mm) 8 8
W Pin1 (mm) Quadrant 16 16 Q1 Q1
CDCU877BZQLR CDCU877BZQLT
ZQL ZQL
52 52
SITE 60 SITE 60
4.8 4.8
7.3 7.3
1.5 1.5
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Feb-2008
Device CDCU877BZQLR CDCU877BZQLT
Package ZQL ZQL
Pins 52 52
Site SITE 60 SITE 60
Length (mm) 342.9 342.9
Width (mm) 345.9 345.9
Height (mm) 28.58 28.58
Pack Materials-Page 2
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